Switching power supply device

ABSTRACT

In some aspects of the invention, a zero current detecting circuit of a switching power supply device detects a gradient of the current flowing in an inductor in the OFF state of the switching element and detects the timing at which the current through the inductor becomes zero corresponding to the detected gradient of the inductor current. Specifically, the zero current detecting circuit receives a signal for controlling ON/OFF driving of the switching element and a voltage signal proportional to the current flowing through the inductor in an OFF state of the switching element. The voltage signal can be compared sequentially with first and second comparison reference voltages to control charging and discharging of a capacitor. Further, the zero current detecting circuit can detect a timing at which the charging and discharging voltage of the capacitor as the timing of zero current flowing through the inductor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to switching power supply devicesthat receive a rectified AC voltage and deliver a stable DC voltage.

2. Description of the Related Art

A power factor correction (PFC) converter of a step-up chopper type, atype of switching power supply device, generates a stable DC outputvoltage while generating an input current proportional to an inputvoltage utilizing self-excited oscillation of an inductor. The PFCconverter has excellent characteristics including small-size, highefficiency, and production at a low cost. FIG. 4 shows a schematicconstruction of this type of switching power supply device, which is apower factor correction converter, in which the reference symbol BDdesignates a rectifier circuit that rectifies an AC power given from anAC power supply through an input filter F and delivers the rectifiedvoltage to the switching power supply device.

This switching power supply device is provided with an inductor Lconnected to the rectifier circuit BD and a switching element Q thatforms a current path from the rectifier circuit BD through the inductorL in the ON state of the switching element Q. The switching power supplydevice is further provided with a diode D that forms a current pathbetween the inductor L and an output capacitor C2 in the OFF state ofthe switching element Q and a control circuit CONT that ON/OFF drivesthe switching element Q to control the current flowing through theinductor L. The symbol C1 designates an input capacitor.

The switching element Q provides the inductor L with a currentproportional to the input voltage applied to the switching power supplydevice in the ON state of the switching element Q. The current flowingthrough the inductor L, inductor current, rises from zero over the ONperiod of the switching element Q. Upon turning OFF of the switchingelement Q, the voltage across the inductor L changes its polarity andthe inductor current is delivered to the output capacitor C2 in theoutput side through the diode D. When the inductor current flowing outfrom the inductor L becomes zero, the switching element Q is turned ONagain to transfer to the next operation cycle. This procedure isrepeated. Japanese Unexamined Patent Application Publication No.2010-220330 (also referred to herein as “Patent Document 1”) andJapanese Unexamined Patent Application Publication No. 2011-103737 (alsoreferred to herein as “Patent Document 2”) disclose this kind ofprocedure.

The control circuit CONT for conducting the ON/OFF control of theswitching element Q is a power supply driving IC to drive directly aMOS-FET used for the switching element Q. The control circuit CONTcomprises an error detector 11 for detecting an error Comp (comparisonreference voltage) that is a difference between an output voltage Vodetected by division with series-connected resistors R1 and R2, and apreset target output voltage. An ON width generating circuit 12indicated in FIG. 4 generates a signal ‘OFF’ that determines an ON widthTon of the switching element Q, which is a MOS-FET, based on the errorComp detected by the error detector 11 and delivers the signal ‘OFF’ toa flip-flop 13 to reset the flip-flop.

The flip-flop 13 is set to make the output q thereof High and reset tomake the output q Low. Receiving the output q from the flip-flop 13, adriving circuit 14 ON/OFF drives the switching element Q. Thus, the ONwidth generating circuit 12 resets the flip-flop 13 with the outputsignal ‘OFF’ to turn OFF the switching element Q.

The control circuit CONT comprises a zero current detecting circuit 15that detects an inductor current Ir from a negative voltage developingacross a resistor R3 inserted in a current path including the inductor Lin particular in a power supply line at the negative side. The zerocurrent detecting circuit 15 compares a voltage Vcs developing acrossthe resistor R3 in proportion to the inductor current Ir with a presetreference voltage Vref, and delivers a zero current detecting signalVzcd when the inductor current Ir reaches the zero level. The referencevoltage Vref is set at as nearly to 0 mV as possible, but generally inthe range of −10 mV to −5 mV in view of power supply noise and circuitparameter variation.

In order to turn ON the switching element Q at the timing of the lowestvoltage, a valley of voltage, undergone by the switching element Q, thezero current detecting signal Vzcd delivered by the zero currentdetecting circuit 15 is delayed by a certain period of time Td in adelay circuit 16 and then given to the flip-flop 13 to set the flip-flop13. Thus, the zero current detecting circuit 15 sets the flip-flop 13with the zero current detecting signal Vzcd and turns ON the switchingelement Q.

The delay of the zero current detecting signal Vzcd in the delay circuit16 is briefly described below. In the OFF state of the switching elementQ, the switching element Q undergoes a high voltage developed at theinductor L, and the inductor current Ir decreases caused by flowing outof the current from the inductor L. When the inductor current Ir returnsto the zero level, a critical point, the zero current detecting circuit15 detects the zero level and delivers the zero current detecting signalVzcd. The inductor current, however, swings further down to negativeside due to resonant oscillation created by the inductance of theinductor L and a parasitic capacitance component in the circuit of thecurrent path including the inductor L. The resonant oscillation alsocauses oscillation in the voltage undergone by the switching element Q.The voltage on the switching element Q is the lowest, a valley ofvoltage oscillation, at the moment when the inductor current Ir changesfrom a negative value to a positive value.

The delay circuit 16 delays the zero current detecting signal Vzcd afterthe zero current detection so as to turn ON the switching element Q atthe timing of the lowest voltage, at a valley of the voltage resonantoscillation, undergone by the switching element Q. The delay time Td ofthe delay circuit 16 is fixedly set in general corresponding to thecircuit parameters of the switching power supply device 1. Owing to thedelay of the zero current detecting signal Vzcd performed in the delaycircuit 16, switching loss on turning ON of the switching element Q islimited to the smallest and the surge current on turning ON of theswitching element Q is also limited to the smallest.

The inductor current Ir varies with time corresponding to ON/OFFoperation of the switching element Q. The rate of the variation, thegradient, depends on the input voltage Vi, the output voltage Vo, andthe inductance of the inductor L, and other parameters in the circuit.The variation of the inductor current Ir also changes a rate ofvariation, a gradient, of the voltage Vcs, which is proportional to theinductor current Ir. As a result, even though the zero current detectingsignal Vzcd is generated based on the comparison between the voltage Vcsand the reference voltage Vref, a discrepancy time Tzcd occurs, as shownin FIG. 5, between the timing at critical point arrival at which theinductor current Ir actually returns to zero from a negative value andthe timing of the lowest voltage, the valley of voltage oscillation, onthe switching element Q.

Because the inductor current Ir varies relating to an instantaneousvalue of the input voltage Vi varying with the phase as shown in FIG. 6,the discrepancy time Tzcd also varies with the input voltage Vi. At aspecific example of phase A with a low input voltage Vi, the gradient ofthe voltage Vcs is large to make the discrepancy time Tzcd small. Incontrast, at the phase D with a high input voltage Vi, the gradient ofthe voltage Vcs is small making the discrepancy time Tzcd large.

Despite this circumstance, the delay time Td is fixedly set in the delaycircuit 16. As a consequence, at a phase of high input voltage Vi, forexample, the switching element Q operates in a continuous mode. Further,even if the delay time Td for the zero current detecting signal Vzcd isadjusted so that the switching element Q is turned ON at the timing ofthe lowest voltage on the switching element Q, the switching element Qis turned ON at a timing earlier or later than the valley of voltageoscillation due to variation of the discrepancy time Tzcd. Therefore,the switching efficiency deteriorates and the power factor decreases.Thus, there exist certain shortcomings in the related art.

SUMMARY OF THE INVENTION

Embodiments of the invention address these and other shortcomings. Someembodiments provide a switching power supply device having a simplestructure that prevents deterioration of efficiency and decrease ofpower factor owing to turning ON of the switching element at the optimumtiming, or at the valley of voltage oscillation, despite variation ofthe input voltage Vi.

Some embodiments do not utilize the voltage Vcs proportional to theinductor current Ir described above but focuses on the gradient of thevoltage Vcs (ramp voltage) to detect the critical point of zero inductorcurrent. Thus, the switching element is turned ON at an appropriatetiming, which is at the valley of voltage oscillation.

A switching power supply device according to some embodiments has: aninductor connected to a rectifier circuit for rectifying AC power, aswitching element forming a current path from the rectifier circuitthrough the inductor in an ON state of the switching element; a diodeforming a current path from the inductor to an output capacitor in anOFF state of the switching element; and a control circuit controllingelectric current flowing through the inductor by ON/OFF driving theswitching element; the control circuit comprising: a zero currentdetecting circuit that detects a gradient of current flowing through theinductor in an OFF state of the switching element and detects a timingof zero current flowing through the inductor corresponding to thedetected gradient to turn ON the switching element, and an ON widthgenerating circuit that compares a comparison reference voltagegenerated based on an output voltage obtained at the output capacitorwith a ramp voltage generated upon turning ON of the switching elementto determine an ON width of the switching element, and turns OFF theswitching element.

Specifically, in some embodiments, the zero current detecting circuitgives an output signal of the detected timing of zero current flowing inthe inductor (inductor current) to an output control circuit for ON/OFFdriving the switching element through a delay circuit for delaying by apredetermined period of time, the output control circuit comprising aflip-flop that is reset by an output of the ON width generating circuitand set by an output of the delay circuit, and a driving circuit thatgenerates a driving signal for the switching element according to anoutput of the flip-flop.

In some embodiments, the zero current detecting circuit receives asignal for controlling ON/OFF driving of the switching element, receivesa voltage signal proportional to the current flowing through theinductor in an OFF state of the switching element, compares the voltagesignal sequentially with a first comparison reference voltage and asecond comparison reference voltage, detects a gradient of the inductorcurrent, and detects the timing of zero current (critical point) flowingthrough the inductor corresponding to the detected gradient of theinductor current.

In some embodiments, the zero current detecting circuit preferablycomprises a capacitor that is charged by a first constant current sourceand discharged by a second constant current source, charges thecapacitor by the first constant current source after the voltage signalproportional to the inductor current exceeds the first comparisonreference voltage until the voltage signal reaches the second comparisonreference voltage, then discharges a charged voltage of the capacitor bythe second constant current source, and detects a timing at which thecharged voltage of the capacitor reaches a third comparison referencevoltage through the discharge as the timing of zero current of theinductor current.

In some embodiments, it is possible that the zero current detectingcircuit detects the gradient of the current flowing through the inductorfrom a differential value of the inductor current in the OFF state ofthe switching element and detects the timing of zero current of theinductor current corresponding to the detected gradient of current.

In some embodiments, in the switching power supply device having theconstruction described above, consideration is directed to a gradient ofthe inductor current to detect the timing of zero current, or thecritical point, flowing in the inductor. Consequently, turning ON of theswitching element can be carried out at the timing of lowest voltage onthe switching element Q irrespective of input voltage variation.Therefore, the switching element does not operate in a continuous modeeven when the input voltage Vi is high. Because the switching element issurely turned OFF at the timing of the lowest voltage, or at the valleyof voltage oscillation, undergone by the switching element, the powerfactor is improved and the switching efficiency does not deteriorate.

In some embodiments, because the zero current detection is conductedwith attention directed to the gradient of the inductor current, theabsolute value of a comparison reference voltage can be high for thezero current detection. Thus, the zero current detection can beperformed at a higher accuracy than in the conventional technology wherethe comparison reference voltage is set at as nearly to zero volts aspossible. Moreover, the zero current detection can be conducted withoutthe influence of the noise superimposed on the power supply line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic construction of a switching power supply deviceof embodiments of the present invention;

FIG. 2 shows an example of construction of the zero current detectingcircuit indicated in FIG. 1;

FIG. 3 is a timing chart showing operation of the zero current detectingcircuit shown in FIG. 2;

FIG. 4 shows a schematic construction of a conventional switching powersupply device;

FIG. 5 illustrates a relationship between the delay time Tzcd and thedetection voltage Vcs proportional to the inductor current to explainthe problem in zero current detection; and

FIG. 6 shows a relationship between the delay time Tzcd and the inputvoltage Vi that varies instantaneous value thereof depending on thephase.

DETAILED DESCRIPTION

The following describes a switching power supply device according to anembodiment of the present invention with reference to the accompanyingdrawings.

FIG. 1 shows a schematic construction of a switching power supply device1, a power factor correction converter, of a step-up chopper type of theembodiment; and FIG. 2 shows a schematic construction of a zero currentdetecting circuit 20 in the switching power supply device 1 shown inFIG. 1. In FIG. 1, the same parts as those in the switching power supplydevice of FIG. 4 are given the same symbols. The input filter F and therectifier circuit BD are omitted in FIG. 1. Redundant repeatingdescription is omitted for the same parts as those in the conventionalswitching power supply device.

The switching power supply device 1 of this embodiment is characterizedin that the output q of the flip-flop 13 is given to the zero currentdetecting circuit 20 that is constructed as shown in FIG. 2. The zerocurrent detecting circuit 20 is constructed so that the zero currentdetection is carried out from a gradient of the voltage Vcs, which is anegative voltage proportional to the inductor current Ir detected withthe resistor R3.

Specifically, the zero current detecting circuit 20 comprises acapacitor 23 (Ccs) that is charged with a constant current Ichg by afirst constant current source 21 and discharged with a constant currentIdis by a second constant current source 22. A first switch 24 controlsthe charging of the capacitor 23 by the first constant current source21; and a second switch 25 controls the discharging of the capacitor 23by the second constant current source 22. The first and the secondswitches 24 and 25 are ON/OFF-controlled reciprocally by the output of aflip-flop (FF) 26. This flip-flop 26 is of a reset preference type.

A first comparator 31 (COM1), which receives the voltage Vcsproportional to the inductor current Ir, is given alternatively a firstcomparison reference voltage Vref1 through a third switch 32 or a secondcomparison reference voltage Vref2 larger than Vref1 through a fourthswitch 33. The third and fourth switches 32 and 33 are also ON/OFFcontrolled reciprocally by the output from the flip-flop 26.

More specifically, when the flip-flop 26 is set, the output Vchg thereofturns ON the first switch 24 to charge the capacitor 23 and also turnsON the fourth switch 33 to give the second comparison reference voltageVref2 to the first comparator 31. When the flip-flop 26 is reset, thesignal Vdis that is the output Vchg of the flip-flop 26 inverted throughthe inverter 27 turns ON the second switch 25 to discharge the capacitor23 and also turns ON the third switch 32 to give the first comparisonreference voltage Vref1 to the first comparator 31.

Consequently, the first comparator 31, in the condition of the flip-flop26 reset, compares the voltage Vcs proportional to the inductor currentIr with the first comparison reference voltage Vref1 and when thevoltage Vcs exceed the first comparison reference voltage Vref1,delivers a signal Vzcdr. The first comparator 31, in the condition ofthe flip-flop 26 set, compares the voltage Vcs proportional to theinductor current Ir with the second comparison reference voltage Vref2,and when the voltage Vcs exceeds the second comparison reference voltageVref2, delivers the signal Vzcdr.

The output signal Vzcdr from the first comparator 31 is deliveredthrough the first gate circuit 34 to the set terminal of the flip-flop26 and at the same time, through the second gate circuit 35 to the resetterminal of the flip-flop 26. The first gate circuit 34 isgate-controlled by the output q of the flip-flop 13 given through aninverter 36. Consequently, the first gate circuit 34 is active in theperiod of time excepting ON state of the switching element Q broughtabout by the output q of the flip-flop 13, or active in the OFF state ofthe switching element Q. The second gate circuit 35 becomes activereceiving an output signal Vccom of a second comparator 37 as describedbelow.

The second comparator 37 compares the charging or discharging voltageVccs across the capacitor 23 with a preset third comparison referencevoltage Vref3, and delivers the signal Vccom when the voltage Vccsexceeds the third comparison reference voltage Vref3. The output signalVccom of the second comparator 37 is delivered through an inverter 38 toa clock terminal of a D type flip-flop 39 as well as used forgate-controlling the second gate circuit 35 as described above. The Dtype flip-flop 39 receives the power supply voltage VDD at the Dterminal thereof and the output q of the flip-flop 13 described earlierat the reset terminal. At a timing of rise up of the signal Vccom givento the clock terminal, the D type flip-flop 39 takes in the power supplyvoltage VDD given to the D terminal and delivers the signal Vzcdindicating zero current detection.

The following describes, with reference to the timing chart shown inFIG. 3, the operation of the zero current detecting circuit 20 havingthe construction described above. In the ON period of the switchingelement Q that is ON/OFF controlled by the output q of the flip-flop 13,an electric current flows into the inductor L. The voltage Vcs, whichdevelops across the resistor R3 in proportion to the inductor currentIr, falls down below zero volts or increases in the absolute value of anegative voltage. Upon turning OFF of the switching element Q, anelectric current flows out of the inductor L. The voltage Vcs, whichdevelops across the resistor R3 in proportion to the inductor current Irrises or decreases in the absolute value of a negative voltage. Theinductor current Ir further swings to the negative side by resonantoscillation caused by the inductance of the inductor L and a parasiticcapacitance component in the circuit of the current path including theinductor L. Accompanying the oscillation of the inductor current, thevoltage Vcs swings to the positive side in a waveform of resonant arc.

In order to detect a gradient of the inductor current Ir in the OFFstate of the switching element Q, the zero current detecting circuit 20compares the negative voltage Vcs proportional to the inductor currentIr with the first comparison reference voltage Vref1 and the secondcomparison reference voltage Vef2 and controls charging and dischargingof the capacitor 23 to generate the signal Vccom having a pulse widthcorresponding to the gradient of the inductor current Ir.

Specifically, in the reset state of the flip-flop 26, the second switch25 is in the ON state keeping the capacitor in a discharging state andthe third switch 32 is in the ON state giving the first referencevoltage Vref1 to the first comparator 31. When the output q of theflip-flop 13 turns to a Low level at a timing t1 in this state, the Highlevel signal inverted from the signal q by the inverter 36 is given tothe first gate circuit 34 as an input signal. When the voltage Vcsexceeds the first comparison reference voltage Vref1 at the timing t2,the output signal Vzcdr from the first comparator 31 is given throughthe first gate circuit 34 to the flip-flop 26 to set the flip-flop 26.

As a consequence of setting of the flip-flop 26, the second and thirdswitches 25 and 32 are turned OFF and instead of these, the first andfourth switches 24 and 33 are turned ON. As a result, the capacitor 23starts to be charged through the first switch 24, and the secondcomparison reference voltage Vref2 is given to the first comparator 31through the fourth switch 33. Accompanying the change of comparisonreference voltage giving to the first comparator 31, the firstcomparator 31 stops delivering the signal Vzcdr. Thus, the signal Vzcdris delivered, when the voltage Vcs exceeds the first comparisonreference voltage Vref1 at the timing t2, as a single shot during thetime, 20 ns for example, corresponding to response delay of the circuit.

The capacitor 23 thus starts to be charged and the charging anddischarging voltage Vccs thereof is given to the second comparator 37and compared with the third comparison reference voltage Vref3 given tothe second comparator 37. The third comparison reference voltage Vref3is set at a value sufficiently lower than the peak value of the chargingand discharging voltage Vccs charged on the capacitor 23. Consequently,the second comparator 37 delivers a signal Vccom at a timing t3immediately after start of charging on the capacitor 23. The signalVccom is given to the second gate circuit 35 as an input signal.

After that, when the voltage Vcs exceeds the second comparison referencevoltage Vref2 at a timing t4, the first comparator 31 delivers thesignal Vzcdr again. The signal Vzcdr is given through the first andsecond gate circuits 34 and 35 to the set terminal and the resetterminal, respectively, of the flip-flop 26. However, the flip-flop 26is of a reset preference type. Thus, the flip-flop 26 is reset onreceiving the signal Vzcdr.

Accompanying the reset of the flip-flop 26, changeover is performed onthe first through fourth switches 24, 25, 32 and 33, and the firstcomparator 31 is given the first comparison reference voltage Vref1again. At the same time, the capacitor 23 stops charging and startsdischarging by the second constant current source 22. The chargingcurrent Ichg onto the capacitor 23 by the first constant current source21 and the discharging current Idis from the capacitor 23 by the secondconstant current source 22 are determined in relation to the first andsecond comparison reference voltages Vref1 and Vref2 as the followingequation, for example.

Idis/Ichg=(Vref1−Vref2)/Vref2

When the charging and discharging voltage Vccs of the capacitor 23decreases to the third comparison reference voltage Vref3 at the timet5, the second comparator 37 stops delivering the signal Vccom. The stopof the output signal Vccom of the second comparator 37 closes the secondgate circuit 35 again. The D type flip-flop 39 receiving the signalVccom through the inverter 38 to the clock terminal takes in the powersupply voltage VDD given to the D terminal due to the stop of the Vccomoutput, and delivers the zero current detecting signal Vzcd.

Consequently, the timing t5 at which the zero current detecting signalVzcd is delivered corresponds to the gradient of the voltage Vcs duringthe period from the timing t2 to the timing t4, where the timing t2 isthe time at which the voltage Vcs proportional to the inductor currentexceeds the first comparison reference voltage Vref1 and the timing t4is the time at which the voltage Vcs exceeds the second comparisonreference voltage Vref2. When the first comparison reference voltageVref1 is set at −20 mV, and the second comparison reference voltageVref2 is set at −10 mV, for example, the zero current detecting signalVzcd is delivered accurately at the timing of zero volts of the voltageVcs proportional to the inductor current Ir.

Thus, the zero current detecting signal Vzcd is delivered at the timingt5 of zero volts of the voltage Vcs from the D type flip-flop 39 or fromthe zero current detecting circuit 20. The zero current detecting signalVzcd is given to the flip-flop 13 after delaying in the delay circuit 16by a certain time Td (see the signal ON in FIG. 3) to reset theflip-flop 13. The setting of the flip-flop 13 turns ON the switchingelement Q at the timing t6. Thus, the switching element Q is turned ONat the timing t6 at which the resonant oscillation voltage is at thevalley thereof and the voltage to which the switching element Q issubjected is the lowest. Therefore, the switching efficiency of theswitching element Q is not deteriorated. The peak of the inductorcurrent Ir can be matched to the instantaneous value corresponding tothe phase of the input voltage Vi and the peak waveform of the inductorcurrent Ir is same as the waveform of the input voltage Vi, so the powerfactor is improved.

At the timing t6 when the switching element Q turns ON, the output qfrom the flip-flop 13 resets the D type flip-flop 39 and makes the firstgate circuit 34 inactive through the inverter 36. At this timing t6, thesecond gate circuit 35 is inactive because of output stop of the signalVccom from the second comparator 37. Thus, upon turning ON of theswitching element Q, the signal Vzcdr is not delivered to the flip-flop26 even though the voltage Vcs proportional to the inductor current Iris higher than the first comparison reference voltage Vref1 and thesignal Vzcdr is on standby at the output terminal of the firstcomparator 31.

Because an electric current flows in to the inductor L again in the ONperiod of the switching element Q, the voltage Vcs proportional to theinductor current Ir decreases, or the absolute value of the negativevoltage increases, from zero volts with increase of the inductor currentIr. When the voltage Vcs decreases below the first comparison referencevoltage Vref1 at the timing t7, the first comparator 31 stops deliveringthe signal Vzcdr. Even though the output of the first comparator 31changes, the state of the flip-flop 26 does not change because the firstand second gate circuits 34 and 35 are both kept closed. Thus, thedischarging state of the capacitor 23 is held over the ON period of theswitching element Q, preparing for charging and discharging in the OFFperiod of the switching element Q.

In some embodiments of the switching power supply device having theabove-described construction, the control circuit thereof accuratelydetects the timing of zero return of the inductor current Ir flowing outof the inductor L during OFF period of the switching element Q.Moreover, the zero current detection can be performed using largethreshold values: first and second comparison reference voltages Vref1and Vref2. Consequently, the noise superimposed on the power supply linedoes not adversely affect the accurate detection of the zero currenttiming. Therefore, the switching power supply device of the inventionachieves improvement in the power factor and switching efficiency aswell as accurate and stable operation.

Embodiments of the invention are not limited to the embodimentsdescribed thus far. The gradient of the inductor current Ir can beobtained, for example, by differentiation processing of the voltage Vcsproportional to the inductor current Ir when the voltage Vcs has reacheda predetermined value. In this case, a zero current detecting signalVzcd is delivered at the timing after passing a certain time determinedcorresponding to the gradient of the inductor current Ir from the timingof reaching the predetermined value of the voltage Vcs.

Although, in the above embodiments, the gradient of the voltage Vcs isdetected by giving alternatively the first and second comparisonreference voltages Vref1 and Vref2 to the first comparator 31, theset/reset control of the flip-flop 26 can be carried out by using twocomparators: a comparator that receives the first comparison referencevoltage Vref1 and another comparator that receives the second comparisonreference voltage Vref2, and the output of the two comparators and theoutput q of the flip-flop 13 are logically processed. Any othermodifications can be done within the scope and spirit of embodiments ofthe invention.

Examples of specific embodiments are illustrated in the accompanyingdrawings. While the invention is described in conjunction with thesespecific embodiments, it will be understood that it is not intended tolimit the invention to the described embodiments. On the contrary, it isintended to cover alternatives, modifications, and equivalents as may beincluded within the spirit and scope of the invention as defined by theappended claims. In the above description, specific details are setforth in order to provide a thorough understanding of embodiments of theinvention. Embodiments of the invention may be practiced without some orall of these specific details. Further, portions of differentembodiments and/or drawings can be combined, as would be understood byone of skill in the art.

This application is based on, and claims priority to, Japanese PatentApplication No. 2012-115273, filed on May 21, 2012, the contents ofwhich are incorporated herein by reference in their entirety.

What is claimed is:
 1. A switching power supply device that has: aninductor connected to a rectifier circuit for rectifying AC power, aswitching element forming a current path from the rectifier circuitthrough the inductor in an ON state of the switching element; a diodeforming a current path from the inductor to an output capacitor in anOFF state of the switching element; and a control circuit controllingelectric current flowing through the inductor by ON/OFF driving theswitching element; the control circuit comprising: a zero currentdetecting circuit that detects a gradient of current flowing through theinductor in an OFF state of the switching element and detects a timingof zero current flowing through the inductor corresponding to thedetected gradient to turn ON the switching element, and an ON widthgenerating circuit that compares a comparison reference voltagegenerated based on an output voltage obtained at the output capacitorwith a ramp voltage generated upon turning ON of the switching elementto determine an ON width of the switching element, and turns OFF theswitching element.
 2. The switching power supply device according toclaim 1, wherein the zero current detecting circuit gives an outputsignal of the detected timing of zero current flowing in the inductor toan output control circuit for ON/OFF driving the switching elementthrough a delay circuit for delaying by a predetermined period of time,the output control circuit comprising a flip-flop that is reset by anoutput of the ON width generating circuit and set by an output of thedelay circuit, and a driving circuit that generates a driving signal forthe switching element according to an output of the flip-flop.
 3. Theswitching power supply device according to claim 1, wherein the zerocurrent detecting circuit receives a signal for controlling ON/OFFdriving of the switching element, receives a voltage signal proportionalto the current flowing through the inductor in an OFF state of theswitching element, compares the voltage signal sequentially with a firstcomparison reference voltage and a second comparison reference voltage,detects a gradient of the current flowing through the inductor, anddetects the timing of zero current flowing through the inductorcorresponding to the detected gradient of current.
 4. The switchingpower supply device according to claim 3, wherein the zero currentdetecting circuit comprises a capacitor that is charged by a firstconstant current source and discharged by a second constant currentsource, charges the capacitor by the first constant current source afterthe voltage signal exceeds the first comparison reference voltage untilthe voltage signal reaches the second comparison reference voltage, thendischarges a charged voltage of the capacitor by the second constantcurrent source, and detects a timing at which the charged voltage of thecapacitor reaches a third comparison reference voltage through thedischarge as the timing of zero current flowing in the inductor.
 5. Theswitching power supply device according to claim 1, wherein the zerocurrent detecting circuit detects the gradient of the current lowingthrough the inductor from a differential value of the current in the OFFstate of the switching element and detects the timing of zero currentflowing through the inductor corresponding to the detected gradient ofcurrent.